1. Technical Field
The present invention relates to a printed circuit board (PCB), and more particularly, to a PCB having a flexible printed circuit.
2. Description
In general, in a printed circuit board (PCB), circuit patterns to electrically connect electronic parts are formed to mount several electronic parts on a flat plate made of phenolic rosins or epoxy rosins etc.
The PCB may be fabricated in a structure having one pattern layer, but may also be fabricated in a laminated multilayer structure. When the PCB requires a capacitance increase in the presence of a spatial limitation, a flexible printed circuit (FPC) is used and a plurality of PCBs are used and are connected mutually.
The FPC transfers signals outputted from a PCB to an external circuit or device, and/or signals outputted from the external circuit or device to the PCB. The external circuit or device may be one or more other PCBs. The FPC is used for a multiplicity of purposes, as a substrate in which a large number of printed wires are arrayed on one face or both faces of the thinned insulation substrate having flexibility.
For example, the FPC allows numerous wires to be arrayed in a high density fashion and can be made in a thin configuration and can be readily installed in a small space due to its flexibility. The FPC also allows an electrical connection between mutually moving units.
A PCB according to prior art will be described referring to the drawings.
FIG. 1 is a perspective view schematically illustrating an example of a PCB having an FPC according to prior art.
Referring to FIG. 1, a first substrate 10, a second substrate 20 and a flexible printed circuit (FPC) are shown.
In the first substrate 10, various electronic parts, e.g., a micro control unit (MCU) and a plurality of semiconductor chips 11-14 etc., are mounted. That is, patterns for the mounting of the MCU and the plurality of semiconductor chips 11-14 are formed in the first substrate 10.
In the second substrate 20, patterns for mounting a plurality of semiconductor chips 21-28 are formed. The second substrate 20 is connected to the first substrate 10 through the FPC.
The FPC is projected from each edge portion of the first and second substrates 10 and 20, to connect the first substrate 10 with the second substrate 20. The FPC provides a signal transmission path between the first substrate 10 and the second substrate 20. The FPC is provided as the signal transmission path between the MCU and the semiconductor chips 11-14 mounted on the first substrate 10 and the semiconductor chips 21-28 mounted on the second substrate 20. In the connected state of the FPC connected to the first substrate 10 or the second substrate 20, the FPC is flexible.
For example, in the first substrate 10 and the second substrate 20 connected through the FPC within a device having a small area, the second substrate 20 may be disposed being spaced from an upper part of the first substrate 10 by a predetermined distance. This example configuration is shown in FIG. 2.
FIG. 2 is a perspective view illustrating a second substrate 20 spaced from an upper part of first substrate 10 shown in FIG. 1.
With reference to FIG. 2, the second substrate 20 connected to the first substrate 10 is spaced a predetermined distance from an upper part of the first substrate 10 through the FPC.
The spaced disposition of the second substrate 20 from the upper part of the first substrate 10 can reduce the area occupied by the PCB.
FIG. 3 is a sectional view taken along a line A1 to A2 shown in FIG. 1, and FIG. 4 is a sectional view of the spaced disposition between the first and second substrates 10 and 20.
Referring to FIGS. 3 and 4, the first and second substrates 10 and 20 are respectively formed of a plurality of pattern layers. The FPC is associated with each layer of the first and second substrates 10 and 20.
Electronic parts are mounted on one face of a first pattern layer L1 of the first substrate 10. The FPC is formed under the first pattern layer L1 to obtain signal transmission with electronic parts mounted on the first substrate 10. An insulation layer 42 is formed between the first pattern layer L1 and the FPC, to be electrically isolated therefrom.
A third pattern layer L3 is formed under the FPC. An insulation layer 44 is formed between the FPC and the third pattern layer L3, to be electrically isolated therefrom. Electronic parts are mounted on one face of the third pattern layer L3. Contact parts formed in the insulation layers 42 and 44 to obtain a signal transmission between pattern layers are not closely related to the present invention, thus they are not shown in the drawings.
The second substrate 20 is formed of a plurality of pattern layers, and the FPC serves as one layer of the plurality of pattern layers as a second pattern layer.
With reference to FIG. 4, in disposing the second substrate 20 spaced from an upper part of the first substrate 10, to prevent a mutual interference between electronic parts mounted on the first and second substrates 10 and 20 or to provide isolation therebetween, an insulation jig is disposed between the first and second substrates 10 and 20, though not shown in the drawings.
Though herein described as an example that the respective first and second substrates 10 and 20 are formed of three-layer structures, it may be formed of the structure of four or more layers.
As described above, in a conventional printed circuit board, the FPC is projected from respective edge portions of the substrates connected mutually through the FPC.
This causes difficulty in reducing a length of the FPC in connecting and disposing one substrate over another substrate.
Such an FPC causes unacceptable impedance matching in the device employing the PCB, and particularly, the impedance matching becomes more difficult when a length of the FPC is increased relatively.
FIG. 5 is a sectional view schematically illustrating an example of a device employing a PCB.
In FIG. 5, the PCB is built in a case or housing 54 of the device employing the PCB.
The PCB is constructed of a first substrate 50 and a second substrate 52 that is connected to the first substrate 50 through the FPC and that is disposed spaced from an upper part of the first substrate 50. Electronic parts (not shown) are mounted on one face or both faces of the respective first and second substrates 50 and 52.
As shown in FIG. 5, when the case 54 of the device employing the PCB has a protuberance 56, and if the FPC is projected from edge portions of the first and second substrates 50 and 52, a length of the FPC should be increased. The length increase of the FPC worsens the impedance mismatching or causes other difficulties.
In particular, signal distortion from the impedance mismatching also causes a setup/hold failure in various signals or a false decision of input level etc.
Hence, to reduce the impedance mismatching it is required to reduce the length of FPC.